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DSP56857 Datasheet(PDF) 457 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 457 Page - Freescale Semiconductor, Inc |
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457 / 662 page  Servicing the Host Interface Host Interface Eight (HI8), Rev. 4 Freescale Semiconductor 16-31 Figure 16-18. HI8 Host Request Structure 16.10.8 Servicing Interrupts When HREQ is connected to the Host Processor interrupt input, the HI8 can request service from the Host Processor by asserting HREQ. HREQ is asserted when TXDE = 1. Generally, servicing the interrupt begins with reading the Interface Status Register (ISG21R) to determine which DSC flag has generated the interrupt. The Host Processor interrupt service routine must read or write the appropriate HI8 register in order to clear the interrupt. HREQ is deasserted when the enabled request is cleared or masked. The Host Processor interrupts are external and use the HREQ pin. HREQ is normally connected to the Host Processor maskable interrupt input. The Host Processor acknowledges host interrupts by executing an interrupt service routine. The two LSBs (RXDF and TXDE) of the Interrupt Status Register may be tested by the Host Processor to determine the interrupt source. Please refer to Figure 16-18. The Host Processor interrupt service routine must read or write the appropriate HI8 register in order to clear the interrupt. HREQ is deasserted when one of the following occurs: • The enabled request is cleared or masked • The DSC is reset 76 5 432 10 RXDF TXDE TRDY HF2 HF3 DMA HREQ ISR 765 432 10 RRE Q TRE Q HLEND HF0 HF1 HM0 HM1 INIT ICR Host Request Asserted HRRQ HREQ HTRQ Status Enable Reserved HF3 TXDE HF3 |
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