DSP56857 datasheet(458/662 Pages) FREESCALE

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Servicing the Host Interface

5685X Digital Signal Controller User Manual, Rev. 4

16-32

Freescale Semiconductor

In the case where the Host Processor is a member of the MC680XX family, servicing the interrupt

starts by asserting HREQ to interrupt the processor. The Host Processor then acknowledges the

interrupt by asserting HACK. When HREQ and HACK are simultaneously asserted, the contents

of the IVR are placed on the Host data bus. This vector tells the Host Processor which routine to

use to service the HREQ interrupt.

16.10.9 Host Side DMA Mode Operation

The Host DMA mode allows the transfer of 8-bit or 16-bit data between the DSC HI8 and an

external DMA controller. The HI8 provides the synchronization logic between the two

asynchronous processor systems. The DSC Side of the interface is serviced by any appropriate

servicing mechanism such as polling, interrupts, or DMA transfer.

The external DMA controller provides the transfers between the DSC HI8 registers and the

external DMA memory. The external DMA controller must provide the address to the external

DMA memory. The address of the selected HI8 register is provided by a DMA address counter in

the DSC HI8.

16.10.9.1 Host-to-DSC Host Interface Action

The following four procedure outlines the steps the HI8 hardware takes to transfer DMA data

from the Host data bus to DSC memory.

1. Assert the Host Request HREQ output pin when the transmit byte registers TXH/TXL are

empty. This always occurs in Host-to-DSC DMA mode when

TXDE = 1.

2. Write the selected transmit byte register from the Host data bus when the HACK input pin

is asserted by the DMA controller. Deassert the HREQ pin.

3. If the highest register address has not been reached, such as TXDE = 1, post-increment the

DMA address counter to select the next register. Wait until HACK is deasserted then go to

Step 1.

4. If the highest register address has been reached, such as TXDE = 0, load the DMA address

counter with the value in HM1 and HM0 and transfer the transmit byte registers

TXH:TXL to the Host Receive Data Register HRX when HRDF = 0. This sets HRDF = 1.

Wait until HACK is deasserted then go to Step 1.

Note:

The DSC-to-Host data transfers can occur normally in the channel not used for DMA

except when the Host must use polling and not interrupts.

Note:

The transfer of data from the TXH/TXL register to the HRX register automatically

loads the DMA address counter from the HM1 and HM0 bits in the DMA

Host-to-DSC mode.

DSP56857 Datasheet(PDF) 458 Page - Freescale Semiconductor, Inc