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DSP56857 Datasheet(PDF) 481 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 481 Page - Freescale Semiconductor, Inc |
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481 / 662 page ![]() TAP Controller JTAG Port, Rev. 4 Freescale Semiconductor 17-19 * Test mode 17.8 TAP Controller The TAP Controller is a synchronous 16-bit finite state machine illustrated in Figure 17-7. It responds to changes at the TMS and TCK pins. Transitions from one state to another will occur on the rising edge of TCK. The value shown adjacent to each state transition represents the signal present on TMS at the time of a rising edge of TCK. The TDO pin will remain in the high impedance state except during the Shift-DR and Shift-IR TAP Controller states. In these controller states, TDO will update on the falling edge of TCK. TDI is sampled on the rising edge of TCK. The TAP Controller will execute the last instruction decoded until a new instruction is entered at the Update-IR state, or Test-Logic-Reset is entered. 253 SC02 Input/Output BC_7 121 121 93 97 136 E6 254 Pull-up BC_1 255 Control BC_2 256 D11 Input/Output BC_7 122 122 94 — 137 D5 257 Pull-up BC_1 258 Control BC_2 259 D12 Input/Output BC_7 123 123 95 — 138 B4 260 Pull-up BC_1 261 Control BC_2 262 D13 Input/Output BC_7 126 126 98 — 142 C4 263 Pull-up BC_1 264 Control BC_2 265 D14 Input/Output BC_7 127 127 99 — 143 F6 266 Pull-up BC_1 267 Control BC_2 268 D15 Input/Output BC_7 128 128 100 — 144 B3 269 Pull-up BC_1 270 Control BC_2 Table 17-5. BSR Contents for 5685x (Continued) Bit Number Pin/Bit Name Pin Type BSR Cell 853 Pin Number (128 LQFP Package) 854 Pin Number (128 LQFP Package) 855 Pin Number (100 LQFP Package) 857 Pin Number (100 LQFP Package) 858 Pin Number (144 LQFP Package) 858 Pin Number (144 MAPBGA Package) |
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