DSP56857 datasheet(483/662 Pages) FREESCALE

483 / 662 page

TAP Controller

JTAG Port, Rev. 4

Freescale Semiconductor

17-21

4. The EOnCE module registers and commands are read and written through the JTAG pins

using the shift-DR-scan path.

Asserting the JTAG’s TRST pin asynchronously forces the JTAG state machine into the

test-logic-reset state.

17.8.1 Operation

All state transitions of the TAP Controller occur based on the value of TMS at the time of a rising

edge of TCK. Actions of the instructions occur on the falling edge of TCK in each controller state

illustrated in Figure 17-1.

17.8.1.1 Test Logic Reset (pstate = F)

During Test-Logic-Reset all JTAG test logic is disabled so the chip can operate in a normal

mode. This is achieved by initializing the Instruction Register (IR) with the IDCODE instruction.

By holding TMS high for five rising edges of TCK, the device will always remain in

Test-Logic-Reset no matter what state the TAP Controller was in previously.

17.8.1.2 Run-Test-Idle (pstate = C)

Run-Test-Idle is a controller state between scan operations. EOnCE entered, the controller will

remain in the Run-Test-Idle mode as long as TMS is held low. When TMS is high and a rising

edge of TCK occurs, the controller moves to the Select-DR state.

17.8.1.3 Select Data Register (pstate = 7)

The Select-DR state is a temporary state. In this state, all Test Data registers selected by the

current instruction retains their previous states. If TMS is held low and a rising edge of TCK

occurs when the controller is in this state, the controller moves into the Capture-DR state and a

scan sequence for the selected Test Data register is initiated. If TMS is held high and a rising

edge of TCK occurs, the controller moves to the Select-IR state.

17.8.1.4 Select Instruction Register (pstate = 4)

The Select-IR state is a temporary state. In this state, all Test Data registers selected by the

current instruction retain their previous states. If TMS is held low and a rising edge of TCK

occurs when the controller is in this state, the controller moves into the Capture-IR state and a

scan sequence for the instruction register is initiated. If TMS is held high and a rising edge of

TCK occurs, the controller moves to the Test-Logic-Reset state.

DSP56857 Datasheet(PDF) 483 Page - Freescale Semiconductor, Inc