DSP56857 datasheet(484/662 Pages) FREESCALE

484 / 662 page

TAP Controller

5685X Digital Signal Controller User Manual, Rev. 4

17-22

Freescale Semiconductor

17.8.1.5 Capture Data Register (pstate = 6)

In this controller state, data may be parallel loaded into test registers selected by the current

instruction on the rising edge of TCK. If a test data register selected by the current instruction

does not have a parallel input, the register retains its previous value.

17.8.1.6 Shift Data Register (pstate = 2)

In this controller state, the Test Data register is connected between TDI and TDO. This data is

then shifted one stage towards its serial output on each rising edge of TCK. The TAP Controller

will remain in this state while TMS is held at a low. When a one is applied to TMS and a positive

edge of TCK occurs the controller will move to the Exit1-DR state.

17.8.1.7 Exit1 Data Register (pstate = 1)

This is a temporary controller state. If TMS is held high, and a rising edge is applied to TCK

while in this state causes the controller to advance to the Update-DR state. This terminates the

scanning process.

17.8.1.8 Pause Data Register (pstate = 3)

This controller state allows shifting of the Test Data register in the serial path between TDI and

TDO to be temporarily halted. All test data registers selected by the current instruction retain

their previous state unchanged. The controller remains in this state while TMS is held low. When

TMS goes high and a rising edge is applied to TCK, the controller advances to the Exit2-DR

state.

17.8.1.9 Exit2 Data Register (pstate = 0)

This is a temporary controller state. If TMS is held high, and a rising edge is applied to TCK

while it is in this state, the scanning process terminates and the TAP Controller advances to the

Update-DR state. If TMS is held low and a rising edge of TCK occurs, the controller advances to

the Shift-DR state.

17.8.1.10 Update Data Register (pstate = 5)

All boundary scan register contain a two stage data register. It isolates the shifting and capturing

of data on the peripheral from what is applied to internal logic during scan mode. This register is

the second stage, or parallel output, and it is used to apply a stimulus to internal logic. Data is

latched on the parallel output of these Test Data registers from the Shift register path on the

falling edge of TCK in the Update-DR state. On a rising edge of TCK, the controller advances to

the Select_DR state if TMS is held high or the Run-Test-Idle state If TMS is held low.

DSP56857 Datasheet(PDF) 484 Page - Freescale Semiconductor, Inc