DSP56857 datasheet(574/662 Pages) FREESCALE

574 / 662 page

Application:

Date:

Programmer:

Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-72

Preliminary

ESSI Control Register 2 (SCR2)

5 of 16

Bits

Name

Description

RIE

Receive Interrupt Enable

This control bit allows interrupting the program controller

Receive FIFO is disabled: No interrupt is generated

Receive FIFO is disabled: Interrupt is generated if the RDR flag in the SSR is set

Receive FIFO is enabled: No interrupt is generated

Receive FIFO is enabled: Interrupt is generated if the RFF flag in the SSR is set

TIE

Transmit Interrupt Enable

This control bit provides program controller interruption

Transmit FIFO is disabled: No interrupt is generated

Transmit FIFO is disabled: Interrupt is generated if the TDE flag in the SSR is set

Transmit FIFO is enabled: No interrupt is generated

Transmit FIFO is enabled: Interrupt is generated if the TFE flag in the SSR is set

Receive Enable

This control bit enables the receive portion of the ESSI

Receiver is disabled by inhibiting data transfer into the SRX

Receiver portion of the ESSI is enabled and received data will be processed

beginning with the next frame sync

TE0

Transmit Enable 0

This control bit enables the transfer of the contents of the STX0 register to its TXSR0

The transmitter continues to send data in TXSRO, then transmitter is disabled

On the next frame boundary, the transmit 0 portion of the ESSI is enabled

TE1

Transmit Enable 1

This control bit enables the transfer of the contents of the STX1 register to its TXSR1

Transmitter continues to send data currently in TXSR1, then disables transmitter

On the next frame boundary, the transmit 1 portion of the ESSI is enabled

TE2

Transmit Enable 2

This control bit enables the transfer of the contents of the STX2 register to its TXSR2

Transmitter continues to send data currently in TXSR2, then disables transmitter

On the next frame boundary, the transmit 2 portion of the ESSI is enabled

ESSI Control

Base + $5

Bits

Read

RIE

TIE RE TE0 TE1 TE2

SYN TSHFD TSCKP ESSIEN NET TFSI TFSL TEFS

Write

Reset

00000

ESSI

denotes Reserved Bits

See the following page for continuation of this register

DSP56857 Datasheet(PDF) 574 Page - Freescale Semiconductor, Inc

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