DSP56857 datasheet(576/662 Pages) FREESCALE

576 / 662 page

Application:

Date:

Programmer:

Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-74

Preliminary

7 of 16

ESSI Control Register 3 (SCR3)

denotes Reserved Bits

ESSI Control

Base + $6

Bits

Read

DIV4DIS RSHFD RSCKP RDMAE TDMAE RFSI RFSL REFS RFEN TFEN INIT

SYN

RST

RLIE TLIE

Write

Reset

Bits

Name

Description

DIV4DIS

Divider 4 Disable

FIX_CLK is equal to the IP_CLK/4 for both transmitter and receiver clock generator circuits

FIX_CLK is equal to the IP_CLK

RSHFD

Receive Shift Direction

This control bit determines if MSB or LSB is received first for the receive section

Data received MSB first

Data received LSB first

RSCKP

Receive Clock Polarity

This control bit determines if bit clock edge is used to capture data for the receive section

Captured data during clock falling edge

Capture data input during rising edge of the clock

RDMAE

Receive DMA Enable

This bit allows the ESSI to request a DMA module transfer of received data

If receive FIFO is disabled: No DMA transfer is requested

If receive FIFO is disabled: DMA request is generated when the ESSI RDR bit is set

If receive FIFO is enabled: No DMA transfer is requested

If receive FIFO is enabled: DMA request is generated when the ESSI FRR bit in SSR is set

TDMAE

Transmit DMA Enable

This bit allows the ESSI to request a DMA transfer for the next data to transmit

If transmit FIFO is disabled: No DMA transfer is requested

If transmit FIFO is disabled: DMA request is generated when the ESSI TDE bit in TDE is set

If transmit FIFO is enabled: No DMA transfer is requested

If transmit FIFO is enabled: DMA request is generated when the ESSI TFE bit in SSR is set

RFSI

Receive Frame Sync Invert

This bit selects the logic of frame sync I/O for the receive section

Frame sync is active high

Frame sync is active low

See the following page for continuation of this register

ESSI

DSP56857 Datasheet(PDF) 576 Page - Freescale Semiconductor, Inc

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