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DSP56857 Datasheet(PDF) 575 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 575 Page - Freescale Semiconductor, Inc |
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575 / 662 page  Application: Date: Programmer: Sheet C 56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4 B-73 Freescale Semiconductor Preliminary ESSI Control Register 2 (SCR2) continued Bits Name Description 7 SYN Synchronous Mode This control bit enables the Synchronous mode of operation 6 TSHFD Transmit Shift Direction This bit controls whether the MSB or LSB is transmitted first for the transmit section 0 MSB is transmitted first 1 LSB is transmitted first 5 TSCKP Transmit Clock Parity This control bit determines which bit clock edge is used to clock out data in the transmit 0 Data is clocked out on the rising edge of the bit clock 1 Falling edge of the bit clock is used to clock the data out 4 ESSIEN ESSI Enable This control bit enables and disables the ESSI 0 The ESSI is disabled 1 The ESSI is enabled 3 NET Network Mode This control bit selects the operational mode of the ESSI 0 Normal mode is selected 1 Network mode is selected 2 TFSI Transmit Frame Sync Invert This control bit selects the logic of frame sync I/O 0 Frame sync is active high 1 Frame sync is active low 1 TFSL Transmit Frame Sync Length This control bit selects the length of the frame sync signal to be generated or recognized 0 A one-word long frame sync is selected 1 A one-bit long frame sync is selected 0 TEFS Transmit Early Frame Sync This bit controls when the frame sync is initiated for the transmit and receive sections 0 Frame sync is initiated as the first bit of data is transmitted 1 Frame sync is initiated one bit before the data is transmitter ESSI 6 of 16 ESSI Control Register 2 (SCR2) Base + $5 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read RIE TIE RE TE0 TE1 TE2 SYN TSHFD TSCKP ESSIEN NET TFSI TFSL TEFS Write Reset 00000 0 0 0 0 0 0 0 0 0 0 0 denotes Reserved Bits |
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