PIC18F4520ESLASHMLQTP datasheet(215/390 Pages) MICROCHIP

215 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 213

PIC18F2420/2520/4420/4520

18.2.2

EUSART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 18-6.

The data is received on the RX pin and drives the data

recovery block. The data recovery block is actually a

high-speed shifter operating at x16 times the baud rate,

whereas the main receive serial shifter operates at the

bit rate or at FOSC. This mode would typically be used

in RS-232 systems.

To set up an Asynchronous Reception:

Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

Enable the reception by setting bit CREN.

Flag bit, RCIF, will be set when reception is

complete and an interrupt will be generated if

enable bit, RCIE, was set.

Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

enable bit CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

18.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

Set the RX9 bit to enable 9-bit reception.

Set the ADDEN bit to enable address detect.

Enable reception by setting the CREN bit.

The RCIF bit will be set when reception is

complete. The interrupt will be Acknowledged if

the RCIE and GIE bits are set.

Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

Read RCREG to determine if the device is being

addressed.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

FIGURE 18-6:

EUSART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

Baud Rate Generator

Pin Buffer

and Control

SPEN

Data

Recovery

CREN

OERR

FERR

RSR Register

MSb

LSb

RX9D

RCREG Register

FIFO

Interrupt

RCIF

RCIE

Data Bus

÷ 64

÷ 16

Stop

Start

(8)

RX9

• • •

SPBRG

SPBRGH

BRG16

÷ 4

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