S1T8825B

1.3GHZ DUAL PLL

8

TEST MODE AND LOCK DETECTOR OUTPUT (T, LD1, LD2)

When T is normal “0”, LD (Pin5) state is varied by controlling “SB1”, “SB2”, “LD1” and “LD2”.

When T is high “1”, LD (Pin5) state is changed to be useful for test

T

SB1

SB2

LD1

LD2

LD Output State

0

0

0

00

low

0

1

channel2

1

0

channel1

1

1

channel1. AND. channel2

1

00

low

0

1

high

1

0

channel1

1

1

channel1

1

0

00

low

0

1

channel2

1

0

high

1

1

channel2

1

00

low

0

1

high

1

0

high

1

1

high

1

10

00

low

0

1

pres2

10

fpll2

11

fref

01

00

div4

0

1

pres1

10

fpll1

1

1

fosc/2

11

××

low

00

××

low