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GD25LB128DVJS Datasheet(PDF) 65 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LB128DVJS Datasheet(HTML) 65 Page - GigaDevice Semiconductor (Beijing) Inc. |
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65 / 75 page  1.8V Uniform Sector Dual and Quad Serial Flash GD25LB128D 65 (T= -40℃~105℃, VCC=1.65~2.0V, CL=30pf) Symbol Parameter Min. Typ. Max. Unit. fC Serial Clock Frequency For: all command except for 03H 104 MHz fR Serial Clock Frequency For: Read (03H) 80 MHz tCLH Serial Clock High Time 4 ns tCLL Serial Clock Low Time 4 ns tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (Read/Write) 20 ns tSHQZ Output Disable Time 6 ns tCLQX Output Hold Time 1.2 ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time 2 ns tCLQV Clock Low To Output Valid 7 ns tDP CS# High To Deep Power-Down Mode 20 μs tRES1 CS# High To Standby Mode Without Electronic Signature Read 20 μs tRES2 CS# High To Standby Mode With Electronic Signature Read 20 μs tRST CS# High To Next Command After Reset (Except From Erase) 30 μs tRST_E CS# High To Next Command After Reset (From Erase) 12 ms tSUS CS# High To Next Command After Suspend 20 us tRS Latency Between Resume And Next Suspend 100 μs tW Write Status Register Cycle Time 5 30 ms tPP Page Programming Time 0.5 2.4 ms tSE Sector Erase Time 70 400 ms tBE1 Block Erase Time (32K Bytes) 0.16 1.2 s tBE2 Block Erase Time (64K Bytes) 0.3 2.4 s tCE Chip Erase Time (GD25LB128D) 50 120 s Note: 1. Typical value tested at T = 25℃. 2. Value guaranteed by design and/or characterization, not 100% tested in production. |
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