ADF5902 datasheet(11/39 Pages) AD

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Data Sheet

ADF5902

Rev. 0 | Page 11 of 39

THEORY OF OPERATION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 17. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This configuration ensures that there is no loading of

the REFIN pin on power-down.

BUFFER

TO R COUNTER

REFIN

100kΩ

NC1

SW2

SW3

NO2

NC1

1NC = NORMALLY CLOSED

2NO = NORMALLY OPEN

SW1

POWER-DOWN

CONTROL

Figure 17. Reference Input Stage

RF INT DIVIDER

The RF INT counter allows a division ratio in the RF feedback

counter. Division ratios from 75 to 4095 are allowed.

INT, FRAC, AND R RELATIONSHIP

Generate the RF VCO frequency (RFOUT) using the INT and

FRAC values in conjunction with the R counter, as follows:

RFOUT = fPFD × (INT + (FRAC/225)) × 2

(1)

where:

RFOUT is the output frequency of the internal VCO.

fPFD is the phase frequency detector (PFD) frequency.

INT is the preset divide ratio of the binary 12-bit counter

(75 to 4095).

FRAC is the numerator of the fractional division (0 to 225 − 1).

fPFD = REFIN × ((1 + D)/(R × (1 + T)))

(2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit (0 or 1).

R is the preset divide ratio of the binary, 5-bit, programmable

reference counter (1 to 32).

T is the REFIN divide by 2 bit (0 or 1).

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

INT

VALUE

RF N DIVIDER

N = INT + FRAC/225

FROM RF

INPUT STAGE

TO PFD/

CAL BLOCK

N COUNTER

Figure 18. RF N Divider

×2

DOUBLER

5-BIT

COUNTER

÷2

DIVIDER

TO PFD/

CAL BLOCK

REFIN

R DIVIDER

Figure 19. Reference Divider

R COUNTER

The 5-bit R counter allows the input reference frequency (REFIN)

to be divided down to supply the reference clock to the PFD

and VCO calibration block. Division ratios from 1 to 32 are

allowed.

PFD AND CHARGE PUMP

The PFD receives inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 20 shows a simplified sche-

matic of the PFD.

CLR2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 20. PFD Simplified Schematic

The PFD includes a fixed delay element that sets the width of the

antibacklash pulse, which is typically 1 ns. This pulse ensures that

there is no dead zone in the PFD transfer function and provides

a consistent reference spur level.

INPUT SHIFT REGISTER

The ADF5902 digital section includes a 5-bit RF R counter,

a 12-bit RF N counter, and a 25-bit FRAC counter. Data is

clocked to the 32-bit input shift register on each rising edge of

CLK. The data is clocked in MSB first. Data is transferred from

the input shift register to one of 18 latches on the rising edge of

LE. The destination latch is determined by the state of the five

control bits (C5, C4, C3, C2, and C1) in the input shift register.

These are the five LSBs (DB4, DB3, DB2, DB1, and DB0,

respectively), as shown in Figure 2. Table 6 shows the truth table

for these bits. Figure 21 and Figure 22 show a summary of how

the latches are programmed.

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