Data Sheet

ADF5902

Rev. 0 | Page 13 of 39

REGISTER MAPS

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.

REGISTER 0 (R0)

REGISTER 1 (R1)

REGISTER 3 (R3)

REGISTER 4 (R4)

REGISTER 2 (R2)

REGISTER 5 (R5)

REGISTER 6 (R6)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

1

00

0

0

0

0

0

CONTROL

BITS

0

000

1

1

11

1

1

1

Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO

C4(0) C3(0) C2(0) C1(0)

C5(0)

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

11

1

1

11

1

1

CONTROL

BITS

1

1

1

1

0

1

1

1

1

1

1

C4(0) C3(0) C2(0) C1(1)

Tx AMP CAL REF CODE

C5(0)

TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

00

0

0

0

0

0

0

0

CONTROL

BITS

0

0

0

0

0

1

0

AS

AA0 AA0

AC7

AC6

AC5 AC4 AC3 AC2 AC1 AC0

C4(0) C3(0) C2(1) C1(0)

RESERVED

ADC CLOCK DIVIDER

ADC

AVERAGE

C5(0)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

0

0

0

0

0

0

1

1

0

0

0

1

0

0

1

M3

M2

M1

M0

IOL

RC5 RC4 RC3 RC2 RC1 RC0

C4(0) C3(0) C2(1) C1(1)

CONTROL

BITS

RESERVED

C5(0)

READBACK CONTROL

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

00

0

0

00

00

AB9

AB14 AB13 AB12 AB11 AB10

AB8

AB7

AB6

AB5 AB4 AB3 AB2 AB1 AB0

C4(0) C3(1) C2(0) C1(0)

CONTROL

BITS

RESERVED

00

0

0

RAMP STATUS/ANALOG TEST BUS

C5(0)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

00

N11

RON

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

F24

F23

F22

F21

F20

F19

F18 F17 F16

F15

F14 F13

C4(0) C3(1) C2(0) C1(1)

CONTROL

BITS

RESERVED

FRAC MSB WORD

INTEGER WORD

C5(0)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

F0

C4(0) C3(1) C2(1) C1(0)

CONTROL

BITS

FRAC LSB WORD

C5(0)

RESERVED

RESERVED

Figure 21. Register Summary (Register 0 to Register 6)