RTL8100B(L)
2001-11-9
Rev.1.41
21
5.12 Media Status Register
(Offset 0058h, R/W)
This register allows configuration of device and PHY options, and provides PHY status information.
Bit
R/W
Symbol
Description
7
R/W
TXFCE/
LdTXFCE
Tx Flow Control Enable: The flow control is valid in full-duplex
mode only. This register’s default value comes from 93C46.
RTL8100B(L)
Remote
TXFCE/LdTXFCE
ANE = 1
NWAY FLY mode
R/O
ANE = 1
NWAY mode only
R/W
ANE = 1
No NWAY
R/W
ANE = 0 &
full-duplex mode
-
R/W
ANE = 0 &
half-duplex mode
-
invalid
NWAY FLY mode : NWAY with flow control capability
NWAY mode only : NWAY without flow control capability
6
R/W
RXFCE
RX Flow control Enable: The flow control is enabled in full-duplex
mode only. The default value comes from 93C46.
5
-
-
Reserved
4
R
Aux_Status
Aux. Power present Status:
1: The Aux. Power is present.
0: The Aux. Power is absent.
The value of this bit is fixed after each PCI reset.
3
R
SPEED_10
Speed: Set, when current media is 10 Mbps mode. Reset, when current
media is 100 Mbps mode.
2
R
LINKB
Inverse of Link status. 0 = Link OK. 1 = Link Fail.
1
R
TXPF
Set, when RTL8100B(L) sends pause packet. Reset, when
RTL8100B(L) sends timer done packet.
0
R
RXPF
Pause Flag: Set, when RTL8100B(L) is in backoff state because a
pause packet received. Reset, when pause state is clear.
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