RTL8100B(L)
2001-11-9
Rev.1.41
42
♦
The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8100B(L) is in isolation
state, or the PME# can be asserted in current power state.
♦
The Magic Packet pattern matches, i.e. 6 * FFh + MISC(can be none)+ 16 * DID(Destination ID) in any part of a valid
(Fast) Ethernet packet.
Wakeup Frame event occurs only when the following conditions are met:
♦
The destination address of the received Wakeup Frame matches.
♦
The received Wakeup Frame does not contain a CRC error.
♦
The PMEn bit (CONFIG1#0) is set to 1.
The 8-bit CRC* (or 16-bit CRC) of the received Wakeup Frame matches with the 8-bit CRC* (or 16-bit CRC) of the
sample Wakeup Frame pattern received from the local machine’s OS.
The last masked byte** of the received Wakeup Frame matches with the last masked byte** of the sample Wakeup Frame
pattern provided by the local machine’s OS. (In Long Wakeup Frame mode, the last masked byte field is replaced with
the high byte of the 16-bit CRC.)
8-bit CRC:
This 8-bit CRC logic is used to generate an 8-bit CRC from the masked bytes of the received Wakeup Frame packet
within offset 12 to 75. Software should calculate the 8-bit Power Management CRC for each specific sample wakeup
frame and store the calculated CRC in the corresponding CRC register for the RTL8100B(L) to check if there is a
Wakeup Frame packet coming in.
16-bit CRC: (Long Wakeup Frame mode, the mask bytes cover from offset 0 to 127)
Long Wakeup Frame: The RTL8100B(L) also supports 3 long Wakeup Frames. If the range of mask bytes of the
sample Wakeup Frame, passed down by the OS to the driver, exceeds the range from offset 12 to 75, the related
registers of wakeup frame 2 and 3 can be merged to support one long wakeup frame by setting the LongWF (bit0,
CONFIG4). Thus, the range of effective mask bytes extends from offset 0 to 127. The low byte and high byte of the
calculated 16-bit CRC should be put into register CRC2 and LSBCRC2 respectively. The mask bytes (16 bytes)
should be stored to register Wakeup2 and Wakeup3. The CRC3 and LSBCRC3 have no meaning in this case and
should be reset to 0. Long Wakeup Frame pairs are frames 4 and 5, and frames 6 and 7. The CRC5, CRC7,
LSBCRC5, and LSBCRC7 have no meaning in this case and should be reset to 0, if the RTL8100B(L) is set to
support long Wakeup Frames. In this case, the RTL8100B(L) support 5 wakeup frames, that are 2 normal wakeup
frames and 3 long wakeup frames.
** last masked byte:
The last byte of the masked bytes of the received Wakeup Frame packet within offset 12 to 75 (in 8-bit CRC
mode) should match the last byte of the masked bytes of the sample Wakeup Frame provided by the local
machine’s OS.
The PME# signal is asserted only when the following conditions are met:
The PMEn bit (bit0, CONFIG1) is set to 1.
The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
The RTL8100B(L) may assert PME# in current power state, or the RTL8100B(L) is in isolation state. Refer to
PME_Support(bit15-11) of the PMC register in PCI Configuration Space.
Magic Packet, LinkUp, or Wakeup Frame has occurred.
* Writing a 1 to the PME_Status (bit15) of PMCSR register in the PCI Configuration Space will clear this bit and cause
the RTL8100B(L) to stop asserting a PME# (if enabled).
When the RTL8100B(L) is in power down mode, ex. D1-D3, the IO, and MEM are all disabled. After RST# asserted, the power
state must be changed to D0 if the original power state is D3cold. There is no hardware enforced delays at RTL8100B(L)’s power
state. When in ACPI mode, the RTL8100B(L) does not support PME from D0 (owing to the setting of PMC register. This setting
comes from EEPROM).
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