56F8167 datasheet(51/184 Pages) FREESCALE

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Peripheral Memory Mapped Registers

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Power Supervisor

LVI

X:$00 F360

4-36

X:$00 F400

4-37

FlexCAN

X:$00 F800

4-38

FlexCAN2

FC2

X:$00 FA00

4-39

Table 4-10 External Memory Integration Registers Address Map

(EMI_BASE = $00 F020)

Address Offset

Reset Value

CSBAR 0

Chip Select Base Address Register 0

0x0004 = 64K when EXTBOOT = 0 or

EMI_MODE = 0

0x0008 = 1M when EMI_MODE = 1

(Selects entire program space for

SC0)

CSBAR 1

Chip Select Base Address Register 1

0x0004 = 64K when EMI_MODE = 0

0x0008 = 1M when EMI_MODE = 1

(Selects A0 - 19 addressable data

space for CS1)

CSBAR 2

Chip Select Base Address Register 2

CSBAR 3

Chip Select Base Address Register 3

CSBAR 4

Chip Select Base Address Register 4

CSBAR 5

Chip Select Base Address Register 5

CSBAR 6

Chip Select Base Address Register 6

CSBAR 7

Chip Select Base Address Register 7

CSOR 0

Chip Select Option Register 0

0x5FCB programmed for chip select

for program space, word wide, read

and write, 11 waits

CSOR 1

Chip Select Option Register 1

0x5FAB programmed for chip select

for data space, word wide, read and

write, 11 waits

CSOR 2

Chip Select Option Register 2

CSOR 3

Chip Select Option Register 3

CSOR 4

Chip Select Option Register 4

CSOR 5

Chip Select Option Register 5

CSOR 6

Chip Select Option Register 6

CSOR 7

Chip Select Option Register 7

CSTC 0

$10

Chip Select Timing Control Register 0

CSTC 1

$11

Chip Select Timing Control Register 1

Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)

Peripheral

Prefix

Base Address

Table Number

56F8167 Datasheet(PDF) 51 Page - Freescale Semiconductor, Inc

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