56F8167 datasheet(66/184 Pages) FREESCALE

66 / 184 page

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Table 4-27 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F2C0)

Address Offset

COPCTL

Control Register

COPTO

Time Out Register

COPCTR

Counter Register

Table 4-28 Clock Generation Module Registers Address Map

(CLKGEN_BASE = $00 F2D0)

Address Offset

PLLCR

Control Register

PLLDB

Divide-By Register

PLLSR

Status Register

Reserved

SHUTDOWN

Shutdown Register

OSCTL

Oscillator Control Register

Table 4-29 GPIOA Registers Address Map

(GPIOA_BASE = $00 F2E0)

Address Offset

Reset Value

GPIOA_PUR

Pull-up Enable Register

0 x 3FFF

GPIOA_DR

Data Register

0 x 0000

GPIOA_DDR

Data Direction Register

0 x 0000

GPIOA_PER

Peripheral Enable Register

0 x 3FFF

GPIOA_IAR

Interrupt Assert Register

0 x 0000

GPIOA_IENR

Interrupt Enable Register

0 x 0000

GPIOA_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOA_IPR

Interrupt Pending Register

0 x 0000

GPIOA_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOA_PPMODE

Push-Pull Mode Register

0 x 3FFF

GPIOA_RAWDATA

Raw Data Input Register

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56F8167 Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc

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