PCIe Gen 4-5

Clock

Generator

CDCDB2000

20x LP-HSCL Output Buffer

SMBus

Control

OE#

Control

LP-HCSL

PCIe PHY

PCIe PHY

PCIe PHY

PCIe PHY

LP-HCSL

20

PCIe PHY

PCIe PHY

PCIe Device

Side-Band

Interface

Control Interface

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCDB2000

SNAS787 – NOVEMBER 2019

CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1

1 Features

1

•

20 LP-HCSL outputs with integrated 85-

Ω output

terminations

•

8 hardware output enable (OE#) controls

•

Additive phase jitter after DB2000QL filter:

< 0.08ps rms

•

Supports PCIe Gen 4 and Gen 5 Common Clock

(CC) and Individual Reference (IR) architectures

–

Spread spectrum-compatible

•

Cycle-to-cycle jitter: < 50 ps

•

Output-to-output skew: < 50 ps

•

Input-to-output delay: < 3 ns

•

3.3-V core and IO supply voltages

•

Hardware-controlled low power mode (PD#)

•

Side-Band Interface (SBI) for output control in

PD# mode

•

9 selectable SMBus addresses

•

Power consumption: < 600 mW

•

6-mm × 6-mm, 80-pin TLGA/GQFN package

2 Applications

•

Microserver & tower server

•

Storage area network & host bus adapter card

•

Network attached storage

•

Hardware accelerator

3 Description

The

CDCDB2000

is

a

20-output

LP-HCSL,

DB2000QL

compliant,

clock

buffer

capable

of

distributing the reference clock for PCIe Gen 1-5,

QuickPath Interconnect (QPI), UPI, SAS, and SATA

interfaces. The SMBus, SBI, and 8 output enable pins

allow the configuration and control of all 20 outputs

individually.

The

CDCDB2000

is

a

DB2000QL

derivative buffer and meets or exceeds the system

parameters in the DB2000QL specification. The

CDCDB2000 is packaged in a 6-mm × 6-mm

TLGA/GQFN package with 80 leads.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

CDCDB2000

TLGA (80)

6.00 mm × 6.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

CDCDB2000 System Diagram