CKx_P

CKPWRGD_PD#

CKx_N

CLKIN

VDD/VDD_A

10

CDCDB2000

SNAS787 – NOVEMBER 2019

www.ti.com

Product Folder Links: CDCDB2000

Submit Documentation Feedback

Copyright © 2019, Texas Instruments Incorporated

Timing Requirements (continued)

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

MIN

NOM

MAX

UNIT

(1)

TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

(2)

TR = (VILMAX - 0.15) to (VIHMIN + 0.15)

300

ns

1000

SIDE-BAND INTERFACE TIMING

Clock period

40

ns

Setup time to clock

25

Data set up time

10

Data hold time

5

Delay time

25

Propagation delay

4

10

CLK

periods

Clock slew rate

20% - 80%

0.2

3

V/ns

Figure 1. Start-Up With CLKIN Timing Diagram