CS5550 datasheet(11/24 Pages) CIRRUS

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CS5550

DS630F1

This linearity is guaranteed for all available

full-scale input voltage ranges.

Note that until the CS5550 is calibrated (see Cali-

bration) the accuracy of the CS5550 is not guaran-

teed to within ±0.1%. But the linearity of any given

sample of CS5550, before calibration, will be within

±0.1% of reading over the ranges specified, with

respect to the input voltage levels required to

cause full-scale readings in the FILT Registers. Ta-

ble 2 describes linearity + variation specs after the

completion of each successive computation cycle.

3. FUNCTIONAL DESCRIPTION

3.1 Analog Inputs

The CS5550 has two available full-scale differen-

tial input voltage ranges for AIN1±.

The input ranges are the maximum sinusoidal sig-

nals that can be applied to the analog inputs, yet

theses values will not result in full scale registra-

tion.

If the analog inputs are set to 500 mVP-P, only a

250 mVRMS signal will register full scale. Yet it

would not be practical to inject a sinusoidal signal

with a value of 250 mVRMS. When such a sine

wave enters the higher levels of its positive crest

region (over each cycle), the voltage level of this

signal exceeds the maximum differential input volt-

age range of the input channels. The largest sine

wave voltage signal that can be placed across the

inputs, with no saturation is:

which is ~70.7% of full-scale. So for sinusoidal in-

puts at the full scale peak-to-peak level the full

scale registration is ~.707.

3.2 Voltage Reference

The CS5550 is specified for operation with a

+2.5 V reference between the VREFIN and AGND

pins. The converter includes an internal 2.5 V ref-

erence (25 ppm/°C drift) that can be used by con-

necting the VREFOUT pin to the VREFIN pin of the

device. If higher accuracy/stability is required, an

external reference can be used.

3.3 Oscillator Characteristics

XIN and XOUT are the input and output of an in-

verting amplifier to provide oscillation and can be

configured as an on-chip oscillator, as shown in

Figure 2. The oscillator circuit is designed to work

with a quartz crystal or a ceramic resonator. To re-

duce circuit cost, two load capacitors C1 and C2

are integrated in the device. With these load ca-

pacitors, the oscillator circuit is capable of oscilla-

tion up to 20 MHz. To drive the device from an

external clock source, XOUT should be left uncon-

nected while XIN is driven by the external circuitry.

There is an amplifier between XIN and the digital

section which provides CMOS level signals. This

amplifier works with sinusoidal inputs so there are

no problems with slow edge times.

The CS5550 can be driven by an external oscillator

ranging from 2.5 to 20 MHz, but the K divider value

must be set such that the internal DCLK will run

somewhere between 2.5 MHz and 5 MHz. The K

divider value is set with the K[3:0] bits in the Con-

figuration Register. As an example, if XIN = MCLK

= 15 MHz, and K is set to 5, then DCLK is 3 MHz,

which is a valid value for DCLK.

500mV

P-P

= ~176.78mV

RMS

Oscillator

Circuit

DGND

XIN

XOUT

C1 =

22 pF

C2 =

Figure 2. Oscillator Connection

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