CS5550

DS630F1

21

5.2 Offset Registers

Address:

1 (Offset Register - AIN1)

3 (Offset Register - AIN2)

Default** = 0.000

The Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements.

The register is loaded after one computation cycle with the offset when the proper input is applied and the Cal-

ibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read

and stored so the register may be restored with the desired system offset compensation. The value is in the

range ± full scale. The numeric format of this register is two’s complement notation.

5.3 Gain Registers

Address:

2 (Gain Register - AIN1)

4 (Gain Register - AIN2)

Default** = 1.000

The Gain registers are initialized to 1.0 on reset, allowing the device to function and perform measurements.

The Gain registers hold the result of the gain calibrations. If a calibration is performed, the register is loaded after

one computation cycle with the system gain when the proper DC input is applied and the Calibration Command

is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the

register may be restored with the desired system offset compensation. The value is in the range 0.0

≤ Gain <

3.9999.

5.4 Cycle Count Register

Address: 5

Default** = 4000

The Cycle Count Register value (denoted as ‘N’) determines the length of one computation cycle. During con-

tinuous conversions, the computation cycle frequency is (MCLK/K)/(1024

∗N) where MCLK is master clock input

frequency (into XIN/XOUT pins), K is clock divider value (as specified in the Configuration Register), and N is

Cycle Count Register Value.

MSB

LSB

.....

MSB

LSB

.....

MSB

LSB

.....