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AM29BDS643D Datasheet(PDF) 40 Page - Advanced Micro Devices |
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AM29BDS643D Datasheet(HTML) 40 Page - Advanced Micro Devices |
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40 / 46 page  40 Am29BDS643D PRELI M INARY AC CHARACTERISTICS Note: Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 10. Figure 19. Initial Access with Power Saving (PS) Function and Address Boundary Latency CLK AVD# RDY PS Address High-Z High-Z A/DQ0: A/DQ15 PS OE# D0 D1 D2 PS1 PS2 device is programmable from 4 to 7 total cycles during initial access (here, programmable wait state function is set to 02h; 6 cycles total) PS high if data is inverted, low if data is not inverted 2 additional wait states if address is at boundary 1 additional wait state to indicate PS is enabled AVD# low with clock present enables burst read mode Address A16:A21 boundary latency tOE |
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