STM32F469 datasheet(50/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

AN4861

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DocID029237 Rev 2

MPU attributes configuration

In order to prevent graphic performance issues related to the Cortex®-M7 speculative read

accesses, the user should review all the memory map of the application and configure the

MPU according to the hardware. So, the user has to set the following configurations:

•

Define the framebuffer MPU region and the other application MPU regions.

•

MPU must be configured according to the size of the memory used by the application.

•

The MPU attributes of the unused regions must be configured to strongly ordered

execute never (XN). For example, for the Quad-SPI, if an 8 MByte memory is

connected, the remaining 248 MByte unused space (from a total 256 MByte

addressable space) must be set to strongly ordered XN. See example in Section 6.2.7.

•

Prevent the Coretx-M7 speculative read accesses to the external SDRAM/SRAM (if the

FMC swap is enabled, see Figure 29), to do it the SDRAM/SRAM MPU region must be

set to execute never (XN).

•

If the Cortex®-M7 CPU is used for framebuffer processing (writing to SDRAM/SRAM),

the framebuffer region MPU attribute should be set to normal cacheable with read and

write access permission.

Note:

The framebuffer MPU region attribute should be set to execute never since it is only

dedicated for graphical content creation.

Figure 29 describes the STM32F7’s FMC banks and Quad-SPI MPU memory attributes at

default system memory map

STM32F469 Datasheet(PDF) 50 Page - STMicroelectronics