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STM32F469 Datasheet(PDF) 51 Page - STMicroelectronics |
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STM32F469 Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 91 page  DocID029237 Rev 2 51/91 AN4861 Creating a graphical application with LTDC 89 Figure 29. FMC SDRAM and NOR/PSRAM memory swap at default system memory map (MPU disabled) MPU and Cache policy configuration The use of Cortex®-M7 cache allows to boost system and graphic performances. This performance gain is especially seen when CPU is accessing external memories such as SDRAM or Quad-SPI. In a graphical application, when the CPU is used for framebuffer processing, it is recommended to use the cache especially if the framebuffer is located in an external memory like SDRAM or SRAM. In that case user should consider the following points when using the cache: • MPU memory region cacheability As previously illustrated in Figure 29, in the default system memory region MPU attributes, some system memory regions are normal cacheable while others are device non-cacheable. When the CPU is used for framebuffer processing, the user should change the framebuffer region MPU attribute to normal cacheable (or do an FMC swap, see Figure 29). |
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