XRT83SL34 datasheet(4/80 Pages) EXAR

4 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................. 1

APPLICATIONS .............................................................................................................................................. 1

Figure 1. Block Diagram of the XRT83SL34 T1/E1/J1 LIU (Host Mode) ........................................ 1

Figure 2. Block Diagram of the XRT83SL34 T1/E1/J1 LIU (Hardware Mode) ................................ 2

FEATURES .................................................................................................................................................... 2

ORDERING INFORMATION ...................................................................................................................... 3

Figure 3. Pin Out of the XRT83SL34 ................................................................................................. 3

TABLE OF CONTENTS ....................................................................................................... I

PIN DESCRIPTION BY FUNCTION ................................................................................... 4

RECEIVE SECTIONS ...................................................................................................................................... 4

TRANSMITTER SECTIONS .............................................................................................................................. 6

MICROPROCESSOR INTERFACE ...................................................................................................................... 8

JITTER ATTENUATOR .................................................................................................................................. 11

CLOCK SYNTHESIZER .................................................................................................................................. 12

ALARM FUNCTION//REDUNDANCY SUPPORT ................................................................................................. 13

POWER AND GROUND ................................................................................................................................. 17

FUNCTIONAL DESCRIPTION ......................................................................................... 18

MASTER CLOCK GENERATOR ...................................................................................................................... 18

Figure 4. Two Input Clock Source .................................................................................................. 18

Figure 5. One Input Clock Source .................................................................................................. 18

RECEIVER ........................................................................................................................ 19

RECEIVER INPUT ......................................................................................................................................... 19

TABLE 1: MASTER CLOCK GENERATOR ............................................................................................... 19

RECEIVE MONITOR MODE ........................................................................................................................... 20

RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... 20

Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... 20

RECEIVE HDB3/B8ZS DECODER ................................................................................................................ 21

RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 21

Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 21

Figure 8. Receive Clock and Output Data Timing ......................................................................... 21

JITTER ATTENUATOR .................................................................................................................................. 22

GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................. 22

TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ........................................ 22

ARBITRARY PULSE GENERATORFOR T1 AND E1 .......................................................................................... 23

TRANSMITTER ................................................................................................................. 23

DIGITAL DATA FORMAT ............................................................................................................................... 23

TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 23

Figure 9. Arbitrary Pulse Segment Assignment ............................................................................ 23

TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 24

Figure 10. Transmit Clock and Input Data Timing ........................................................................ 24

TABLE 3: EXAMPLES OF HDB3 ENCODING ........................................................................................... 24

TABLE 4: EXAMPLES OF B8ZS ENCODING ........................................................................................... 24

DRIVER FAILURE MONITOR (DMO) .............................................................................................................. 25

TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... 25

TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ........................... 25

TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 26

RECEIVER (CHANNELS 0 - 3) ................................................................................................................... 26

Internal Receive Termination Mode .......................................................................................................... 26

TABLE 6: RECEIVE TERMINATION CONTROL .......................................................................................... 26

Figure 11. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ 27

TABLE 7: RECEIVE TERMINATIONS ....................................................................................................... 28

XRT83SL34 Datasheet(PDF) 4 Page - Exar Corporation

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