XRT83SL34 datasheet(64/80 Pages) EXAR

64 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

TABLE 35: MICROPROCESSOR REGISTER #64, BIT DESCRIPTION

1000000

NAME

FUNCTION

TYPE

RESET

VALUE

BIT #

SR/DR

Single-rail/Dual-rail Select: Writing a “1” to this bit configures

all 8 channels in the XRT83SL34 to operate in the Single-rail

mode.

Writing a “0” configures the XRT83SL34 to operate in Dual-rail

mode.

R/W

ATAOS

Automatic Transmit All Ones Upon RLOS: Writing a “1” to

this bit enables the automatic transmission of All "Ones" data

to the line for the channel that detects an RLOS condition.

Writing a “0” disables this feature.

R/W

RCLKE

Receive Clock Edge: Writing a “1” to this bit selects receive

output data of all channels to be updated on the negative edge

of RCLK.

Wring a “0” selects data to be updated on the positive edge of

RCLK.

R/W

TCLKE

Transmit Clock Edge: Writing a “0” to this bit selects transmit

data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all

channels to be sampled on the falling edge of TCLK_n.

Writing a “1” selects the rising edge of the TCLK_n for sam-

pling.

R/W

DATAP

DATA Polarity: Writing a “0” to this bit selects transmit input

and receive output data of all channels to be active “High”.

Writing a “1” selects an active “Low” state.

R/W

Reserved

GIE

Global Interrupt Enable: Writing a “1” to this bit globally

enables interrupt generation for all channels.

Writing a “0” disables interrupt generation.

R/W

SRESET

Software Reset

µP Registers: Writing a “1” to this bit longer

than 10µs initiates a device reset through the microprocessor

interface. All internal circuits are placed in the reset state with

this bit set to a “1” except the microprocessor register bits.

R/W

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