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PIC16F913E/SS301 Datasheet(PDF) 26 Page - Microchip Technology |
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PIC16F913E/SS301 Datasheet(HTML) 26 Page - Microchip Technology |
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26 / 272 page ![]() PIC16F917/916/914/913 DS41250E-page 24 Preliminary © 2005 Microchip Technology Inc. 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-1. REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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