PIC16F913ESLASHSS301 datasheet(99/272 Pages) MICROCHIP

99 / 272 page

Preliminary

DS41250E-page 97

PIC16F917/916/914/913

CMCON1 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 97h)

8.4

Comparator Outputs

The comparator outputs are read through the

CMCON0 register. These bits are read-only. The

comparator outputs may also be directly output to the

RA4 and RA5 I/O pins. When enabled, multiplexers in

the output path of the RA4 and RA5 pins will switch

and the output of each pin will be the unsynchronized

output of the comparator. The uncertainty of each of

the comparators is related to the input offset voltage

and the response time given in the specifications.

Figure 8-4 and Figure 8-5 show the output block

diagram for Comparator 1 and 2.

The TRIS bits will still function as an output

enable/disable for the RA4 and RA5 pins while in this

mode.

The polarity of the comparator outputs can be changed

using the C1INV and C2INV bits (CMCON0<5:4>).

Timer1 gate source can be configured to use the T1G

pin or Comparator 2 output as selected by the T1GSS

bit (CMCON1<1>). This feature can be used to time

the duration or interval of analog events. The output of

Comparator 2 can also be synchronized with Timer1

by setting the C2SYNC bit (CMCON1<0>). When

enabled, the output of Comparator 2 is latched on the

falling edge of Timer1 clock source. If a prescaler is

used with Timer1, Comparator 2 is latched after the

prescaler. To prevent a race condition, the Comparator

2 output is latched on the falling edge of the Timer1

clock source and Timer1 increments on the rising edge

of its clock source. See (Figure 8-5), Comparator 2

Block

Diagram

and

(Figure 6-1),

Timer1

Block

Diagram for more information.

It is recommended to synchronize Comparator 2 with

Timer1 by setting the C2SYNC bit when Comparator 2

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if Comparator 2 changes

during an increment.

8.5

Comparator Interrupts

The comparator interrupt flags are set whenever there is

a change in the output value of its respective comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON0<7:6>, to

determine the actual change that has occurred. The CxIF

bits, PIR2<6:5>, are the Comparator Interrupt flags. This

bit must be reset in software by clearing it to ‘0’. Since it

is also possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

The

CxIE

bits

(PIE2<6:5>)

and

the

PEIE

bit

(INTCON<6>) must be set to enable the interrupts. In

addition, the GIE bit must also be set. If any of these

bits are cleared, the interrupt is not enabled, though the

CxIF bits will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of CMCON0. This will end the

mismatch condition.

Clear flag bit CxIF

A mismatch condition will continue to set flag bit CxIF.

Reading CMCON0 will end the mismatch condition and

allow flag bits CxIF to be cleared.

U-0

R/W-1

R/W-0

—

T1GSS

C2SYNC

bit 7

bit 0

bit 7-2:

Unimplemented: Read as ‘0’

bit 1

T1GSS: Timer1 Gate Source Select bit

= Timer1 gate source is T1G pin (RC4 must be configured as digital input)

= Timer1 gate source is Comparator 2 Output

bit 0

C2SYNC: Comparator 2 Synchronize bit

= C2 output synchronized with falling edge of Timer1 clock

= C2 output not synchronized with Timer1 clock

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Note:

If a change in the CMCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the Q2

cycle), then the CxIF (PIR2<6:5>) interrupt

flag may not get set.

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