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STM32G071C8 Datasheet(PDF) 99 Page - STMicroelectronics |
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STM32G071C8 Datasheet(HTML) 99 Page - STMicroelectronics |
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99 / 133 page ![]() DS12232 Rev 3 99/133 STM32G071x8/xB Electrical characteristics 106 5.3.24 Characteristics of communication interfaces I2C-bus interface characteristics The I2C-bus interface meets timing requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The timings are guaranteed by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the minimum shown in the following table. tCOUNTER 16-bit counter clock period - 1 65536 tTIMxCLK fTIMxCLK = 64 MHz 0.015625 1024 µs tMAX_COUNT Maximum possible count with 32-bit counter - - 65536 × 65536 tTIMxCLK fTIMxCLK = 64 MHz - 67.10 s 1. TIMx, is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17. Table 66. TIMx(1) characteristics (continued) Symbol Parameter Conditions Min Max Unit Table 67. IWDG min/max timeout period at 32 kHz LSI clock(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF Unit /4 0 0.125 512 ms /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period. |
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