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TP2435 Datasheet(PDF) 1 Page - Microchip Technology |
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TP2435 Datasheet(HTML) 1 Page - Microchip Technology |
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1 / 14 page  2019 Microchip Technology Inc. DS20005961A-page 1 TP2435 Features • Low Threshold • High Input Impedance • Low Input Capacitance • Fast Switching Speeds • Free from Secondary Breakdown • Low Input and Output Leakage Applications • Logic-Level Interfaces (Ideal for TTL and CMOS) • Solid-State Relays • Linear Amplifiers • Analog Switches • Power Management • Telecommunication Switches General Description The TP2435 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Microchip’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Package Type See Table 3-1 for pin information. 3-lead SOT-89 (Top view) GATE SOURCE DRAIN DRAIN P-Channel Enhancement-Mode Vertical DMOS FET |
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