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STM32L021D4 Datasheet(PDF) 81 Page - STMicroelectronics

Part # STM32L021D4
Description  Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AES
PDF  114 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L021D4 Datasheet(HTML) 81 Page - STMicroelectronics

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STM32L021x4
Electrical characteristics
93
Equation 1: RAIN max formula
The simplified formula above (Equation 1) is used to determine the maximum external
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
CADC(3)
Internal sample and hold
capacitor
--
-
8
pF
tCAL(3)
Calibration time
fADC = 16 MHz
5.2
µs
-83
1/fADC
WLATENCY
ADC_DR register write
latency
ADC clock = HSI16
1.5 ADC
cycles + 2
fPCLK cycles
-
1.5 ADC
cycles + 3
fPCLK cycles
-
ADC clock = PCLK/2
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
tlatr(3)
Trigger conversion latency
fADC = fPCLK/2 = 16 MHz
0.266
µs
fADC = fPCLK/2
8.5
1/fPCLK
fADC = fPCLK/4 = 8 MHz
0.516
µs
fADC = fPCLK/4
16.5
1/fPCLK
fADC = fHSI16 = 16 MHz
0.252
-
0.260
µs
JitterADC
ADC jitter on trigger
conversion
fADC = fHSI16
-1
-
1/fHSI16
tS(3)
Sampling time
fADC = 16 MHz
0.093
-
10.03
µs
-
1.5
-
239.5
1/fADC
tSTAB(3)
Power-up time
-
0
0
1
µs
tConV(3)
Total conversion time
(including sampling time)
fADC = 16 MHz
0.875
10.81
µs
-
14 to 173 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 54: RAIN max for fADC = 16
MHz.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 31: Peripheral current
consumption in run or Sleep mode).
3. Guaranteed by design, not tested in production.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 54: RAIN max for
fADC = 16 MHz.
Table 53. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R
AIN
T
S
f
ADC
C
ADC
2
N2
+
()
ln
×
×
---------------------------------------------------------------- R
ADC
–
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