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LAN7430/Y9X Datasheet(PDF) 26 Page - Microchip Technology |
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LAN7430/Y9X Datasheet(HTML) 26 Page - Microchip Technology |
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26 / 77 page ![]() LAN7430/LAN7431 DS00002631D-page 26 2018-2019 Microchip Technology Inc. 4.0 POWER CONNECTIVITY This section details the power connectivity of the LAN7430 and LAN7431 in various configurations. Power sequence timing is detailed in Section 7.6.2, "Power Sequence Timing". 4.1 LAN7430 Power Connectivity The following diagrams illustrate the power connectivity for LAN7430 with on-chip regulators enabled and disabled. FIGURE 4-1: LAN7430 POWER CONNECTIVITY ON-CHIP REGULATORS ENABLED +1.8 V to +3.3 V VDD12CORE Core Logic & Ethernet PHY digital Ethernet PHY Analog 1.0 µF <1 ESR VSS VDD12_SW_OUT AVDD12 Ethernet PHY Bandgap and Osc IO Pads Note: Bypass and bulk caps as needed for PCB. Ferrites on AVDDL and AVDD12 may be combined. VDDVARIO (1 pin) VDD_SW_IN (1 pin) +3.3 V (1 pin) (3 pins) (2 pins) (1 pin) Ethernet PHY PLL (exposed pad) VDD25_REG_OUT (1 pin) VDD12_SW_FB VDD_REG_IN (1 pin) 3.3 / 1.2 OTP VDD_OTP (1 pin) (1 pin) AVDDH AVDDL (2 pins) PCIe PHY VP (1 pin) VPTX (1 pin) VPH (1 pin) 3.3 uH 10 µF <0.05 ESR 0.1uF +3.3 V optional 3.3V PHY operation +1.8 V to +3.3 V IN OUT Internal 1.2 V Switching Regulator FEEDBACK REF IN OUT Internal 2.5 V LDO Regulator ENABLE |
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