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PIC24FJ128GL303 Datasheet(PDF) 1 Page - Microchip Technology |
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PIC24FJ128GL303 Datasheet(HTML) 1 Page - Microchip Technology |
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1 / 424 page  2019-2020 Microchip Technology Inc. DS30010198B-page 1 PIC24FJ128GL306 FAMILY High-Performance CPU • Modified Harvard Architecture • 128 Kbytes Flash Memory • 8 Kbytes SRAM • Up to 16 MIPS Operation @ 32 MHz • 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier • 32-Bit by 16-Bit Hardware Divider • 16-Bit x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture • Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory LCD Display Controller • 32x8 with Up to 256 Pixels • LCD Charge Pump • Core-Independent LCD Animation • Operation in Sleep mode Analog Features • Up to 17-Channel, Software-Selectable, 10/12-Bit Analog-to-Digital Converter: - 12-bit, 350K samples/second conversion rate (single Sample-and-Hold) - 10-bit, 400K samples/second conversion rate (single Sample-and-Hold) - Sleep mode operation - Low-voltage boost for input - Band gap reference input feature - Core-independent windowed threshold compare feature - Auto-scan feature • Three Analog Comparators with Input Multiplexing: - Programmable reference voltage for comparators eXtreme Low-Power Features • Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up • Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals • Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction • Retention Sleep with On-Chip Ultra Low-Power Retention Regulator Functional Safety and Security Peripherals • Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator • Power-on Reset (POR), Brown-out Reset (BOR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Programmable High/Low-Voltage Detect (HLVD) • Flexible Watchdog Timer (WDT) with RC Oscillator for Reliable Operation • Deadman Timer (DMT) for Monitoring Health of Software • Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator • Flash OTP by ICSP™ Write Inhibit • CodeGuard™ Security • ECC Flash Memory (128 Kbytes) with Fault Injection: - Single Error Correction (SEC) - Double Error Detection (DED) • Customer OTP Memory • Unique Device Identifier (UDID) Special Microcontroller Features • Supply Voltage Range of 2.0V to 3.6V • Operating Ambient Temperature Range of -40°C to +125°C • On-Chip Voltage Regulators (1.8V) for Low-Power Operation • Flash Memory: - 10,000 erase/write cycle endurance, typical - Data retention: 20 years minimum - Self-programmable under software control - Flash OTP emulation • 8 MHz Fast RC Internal Oscillator: - Multiple clock divide options - Fast start-up •96 MHz PLL Option • Programmable Reference Clock Output • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via Two Pins • JTAG Boundary Scan Support 16-Bit eXtreme Low-Power Microcontrollers with LCD Controller in Low Pin Count Packages |
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