ADPA7004CHIP-SX datasheet(15/20 Pages) AD

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Data Sheet

ADPA7004CHIPS

Rev. 0 | Page 15 of 20

APPLICATIONS INFORMATION

Basic connections for operating the ADPA7004CHIPS are

shown in Figure 46 and Figure 47. There are eight VDDxA and

VDDxB drain bias pads. To minimize voltage drops in bond

wires and on die traces, all eight pads (VDDxA through VDDxB)

must be used. Each VDDxA and VDDxB line has a 100 pF decoupling

capacitor with adjacent pads sharing larger decoupling capacitors.

The power supply decoupling capacitors shown in Figure 46

represent the configuration that was used to characterize and

qualify the device. It may be possible to reduce the number of

capacitors, but the scope varies from system to system. It is

recommended to first remove or combine the largest capacitors

that are farthest from the device.

All four gate bias voltages pads (VGG1234x) are internally

connected. In contrast to the VDDxA through VDDxB drain bias

lines, the gate bias voltage can be applied through a single pad

on either the north or the south side of the die. Figure 46 shows

the gate bias voltage applied through the VGG1234B pins on the

south side of the die, and Figure 47 shows the gate bias voltage

applied to the VGG1234A pins on the north side of the die. In

both cases, a single 100 pF capacitor must be connected to one

of the gate bias pads on the unused side.

POWER-UP AND POWER-DOWN SEQUENCING

To prevent damage to the ADPA7004CHIPS, follow the power-up

and power-down sequences.

Power-Up Sequence

Take the following steps to power up the device:

Connect all grounds.

Set the gate bias voltages (VGG1234x) to −1.5 V.

Set the drain bias voltages (VDDxA through VDDxB)

to 3.5 V.

Increase the gate bias voltages (VDDxA through VDDxB)

to achieve IDQ = 550 mA.

Apply the RF signal.

Power-Down Sequence

Take the following steps to power down the device:

Turn off the RF signal.

Decrease the gate bias voltages (VGG1234x) to −1.5 V to

reduce IDQ to approximately 0 mA.

Reduce the drain bias voltages (VDDxA through VDDxB)

to 0 V.

Increase the gate bias voltages (VGG1234x) to 0 V.

The VDD = 3.5 V and IDQ = 550 mA bias conditions are

recommended to optimize overall performance. Table 8

summarizes the performance at 60 GHz at other drain current

settings along with the dc quiescent power consumption (dc

power consumption increases with RF applied). In this case,

higher drain current slightly increases output IP3 but has

minimal impact on output P1dB.

RF DETECTOR OPERATION

To achieve a temperature stable RF detector output voltage

(VOUT), subtract the voltage on the VDET pad from the voltage

on the VREF pad, which can be done by using the differential

op-amp circuit shown in Figure 46 and Figure 47.

Table 8. DC Power Consumption Selection Table1, 2

IDQ (mA)

Gain (dB)

Output P1dB (dBm)

Output IP3 (dBm)

PDISS (W)

VGG (V)

450

16.4

30.1

1.6

−0.5

550

22.2

31.0

1.9

−0.4

650

19.5

22.2

31.9

2.3

−0.3

1 Data taken at the following nominal bias conditions: VDD = 3.5 V, TA = 25°C, and frequency = 60 GHz.

2 Adjust VGG1234x between −1.5 V and 0 V to achieve the desired IDQ.

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