Data Sheet

ADIS16446

Rev. 0 | Page 9 of 23

THEORY OF OPERATION

The ADIS16446 is an autonomous system that requires no

user initialization. When the device has a valid power supply,

it initializes itself and starts sampling, processing, and loading

sensor data into the output registers at a sample rate of 819.2 SPS.

DIO1 pulses high after each sample cycle concludes. The SPI

enables simple integration with many embedded processor

platforms, as shown in Figure 9 (electrical connection) and

Table 6 (pin functions). Note that the use of 33 Ω series

resistors placed near the transmitters on the SPI lines shown

in Figure 9 can provide additional signal integrity but are

not required in most applications.

SYSTEM

PROCESSOR

SPI MASTER

ADIS16446

SCLK

CS

DIN

DOUT

SCLK

SS

MOSI

MISO

+3.3V

IRQ

DIO1

(USER-CONFIGURABLE.

FACTORY DEFAULT IS DIO1)

VDD

I/O LINES ARE COMPATIBLE WITH

3.3V LOGIC LINES

6

3

5

4

7

11

14

13

Figure 9. Electrical Connection Diagram

Table 6. Generic Master Processor Pin Names and Functions

Pin Name

Function

SS

Slave select

SCLK

Serial clock

MOSI

Master output, slave input

MISO

Master input, slave output

IRQ

Interrupt request

The ADIS16446 SPI supports full duplex serial communication

(simultaneous transmit and receive) and uses the bit sequence

shown in Figure 10. Table 7 provides a list of the most common

settings used to initialize the serial port of a processor for the

ADIS16446 SPI.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

The ADIS16446 operates as a slave

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), and CPHA = 1 (phase)

MSB First Mode

Bit sequence

16-Bit Mode

Shift register and data length

1

For burst read, SCLK rate ≤ 1 MHz.

DEVICE OPERATION

During normal operation, the ADIS16446 generates a data

ready pulse every time a new sample is available. In the default

configuration, the 819.2 SPS sample clock that generates the

data ready pulse is internally generated, although the user has

the option of synchronizing the data sampling to an external

clock. The ADIS16446 registers are updated when the data

ready signal is inactive. Therefore, the user must not attempt to

read the ADIS16446 registers during this time.

When performing operations such as part configuration, reset,

self test, or flash memory update, the best way to know if the

operation is complete is by monitoring the data ready pulse

because the data ready pulse automatically resumes after the

desired operation completes. Note that excessive SPI transactions

(such as polling a status register) during a self test or flash

memory update delay completion of the task. See the Data

Ready Indicator section for further information on the data

ready indicator.

R/W

R/W

A6

A5

A4

A3

A2

A1

A0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CS

SCLK

DIN

DOUT

A6

A5

D13

D14

D15

NOTES

1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]

IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.

2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.

Figure 10. SPI Communication Bit Sequence