ADIS1644XSLASHFLEX datasheet(10/23 Pages) AD

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ADIS16446

Data Sheet

Rev. 0 | Page 10 of 23

READING SENSOR DATA

The ADIS16446 provides two different options for acquiring

sensor data: the single register and the burst register. A single

requests the contents of the register using the bit assignments in

Figure 10. Bit DC7 to Bit DC0 are don’t cares for a read, and then

the output register contents follow on DOUT during the second

sequence. Figure 11 includes three single register reads in

succession. In this example, the process starts with DIN =

0x0400 to request the contents of XGYRO_OUT, then follows

with 0x0600 to request YGYRO_OUT, and 0x0800 to request

ZGYRO_OUT. Full duplex operation enables processors to

use the same 16-bit SPI cycle to read data from DOUT while

requesting the next set of data on DIN. Figure 12 provides an

example of the four SPI signals when reading XGYRO_OUT in

a repeating pattern.

XGYRO_OUT

DIN

DOUT

YGYRO_OUT

ZGYRO_OUT

0x0400

0x0600

0x0800

Figure 11. SPI Read Example

SCLK

DIN

DOUT

DOUT = 1111 10011101 1010 = 0xF9DA = –1574 LSBs ≥ –62.96°/sec

DIN = 0000 0100 0000 0000 = 0x0400

Figure 12. Example SPI Read, Second 16-Bit Sequence

Burst Read Function

The burst read function provides a way to read all of the data

in one continuous stream of bits (no stall time). As shown in

Figure 13, start this mode by setting DIN = 0x3E00 while

keeping CS low for 8 additional 16-bit read cycles. These

8 cycles produce the following sequence of output registers

on DOUT: DIAG_STAT, XGYRO_OUT, YGYRO_OUT,

ZGYRO_OUT, XACCL_OUT, YACCL_OUT, ZACCL_OUT,

and TEMP_OUT. Note that Figure 13 shows the first, second,

and final bytes of the burst sequence only.

GLOB_CMD

SCLK

DIN

DOUT

XGYRO_OUT

DIAG_STAT

TEMP_OUT

Figure 13. Burst Read Sequence

SPI Read Test Sequence

Figure 14 provides a test pattern for testing SPI communication. In

this pattern, write 0x5600 to the DIN line in a repeating pattern

and raise CS in between each repeating 16-bit sequence. CS must

remain high for at least the tSTALL time listed in Table 2 in between

each 16-bit sequence. Starting with the second 16-bit sequence,

DOUT produces the contents of the PROD_ID register (see

Table 22), 0x403E.

DOUT = 0100 0000 001111110 = 0x403E = 16446 DECIMAL

DIN = 0101 0110 0000 0000 = 0x5600

SCLK

DIN

DOUT HIGH-Z

HIGH-Z

Figure 14. SPI Test Read Pattern DIN = 0x5600, DOUT = 0x403E

DEVICE CONFIGURATION

The control registers in Table 8 provide users with a variety of

configuration options. The SPI provides access to these registers,

one byte at a time, using the bit assignments in Figure 10. Each

and Bits[15:8] represent the upper address. Figure 15 provides an

example of writing 0x04 to Address 0x36 (SMPL_PRD, Bits[15:8],

using DIN = 0xB704. This example reduces the sample rate by a

factor of eight (see Table 28).

SCLK

DIN

DIN = 1011 0110 0000 0100 = 0xB604, WRITES 0x04 TO ADDRESS 0x36.

Figure 15. Example SPI Write Sequence

Dual Memory Structure

Writing configuration data to a control register updates its SRAM

contents, which are volatile. After optimizing each relevant control

0xBE08) to backup these settings in the nonvolatile flash memory.

The flash backup process requires a valid power supply level for

the entire process time, 75 ms. Table 8 provides a user register

memory map that includes a flash backup column. A yes in this

column indicates that a register has a mirror location in flash and,

when backed up properly, it automatically restores itself during

startup or after a reset. Figure 16 provides a diagram of the dual

memory structure used to manage operation and store critical

user settings.

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

MANUAL

FLASH

BACKUP

START-UP

RESET

VOLATILE

SRAM

SPI ACCESS

Figure 16. SRAM and Flash Memory Diagram

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