FXLS8964AFR1 datasheet(22/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

22 / 98

the next 8 SCLK cycles (pulses 17 through 24) output the selected register content on

the SPI_MISO line in MSb first order. The following figure shows the bus protocol for a

single byte read operation.

13 14 15 16

R/W A6 A5 A4 A3 A2 A1 A0

18 19

21 22

23 24

D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

SPI_CS_B

SCLK

SPI_MOSI

SPI_MISO

Figure 14. SPI single byte read protocol diagram (4-wire mode), R/W = 1

Multiple-byte read operations are performed similarly to single-byte reads with additional

bytes read out in multiples of eight SCLK cycles. The register read address is auto-

incremented by FXLS8964AF so that every eighth clock edge will latch the address of the

next sequential register read address. When the desired number of bytes has been read,

a rising edge on SPI_CS_B terminates the transaction.

13 14 15 16

R/W A6 A5 A4 A3 A2 A1 A0

18 19

21 22

23 24

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

28 29 30 31 32

High-Impedance

SPI_CS_B

SCLK

SPI_MOSI

SPI_MISO

Figure 15. SPI multiple byte read protocol diagram (4-wire mode), R/W = 1

11.4 SPI read operations with 3-wire mode

FXLS8964AF can be configured to operate in 3-wire software enabled SPI mode. In

this mode, the SPI_MISO pin is left unconnected and the SPI_MOSI pin becomes a

bidirectional input/output pin (SPI_DATA). Read operations in 3-wire mode are the same

as write operations in 3- and 4-wire modes, except that at the end of the address cycle

(falling edge of clock pulse 16), the SPI_DATA pin automatically switches from an input

to an output and with bit D7 as the current output state.

FXLS8964AFR1 Datasheet(PDF) 22 Page - NXP Semiconductors

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