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Data Sheet

ADIS16467

Rev. C | Page 13 of 34

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI provides access to the user registers (see Table 8).

Figure 26 shows the most common connections between the

ADIS16467 and a SPI master device, which is often an embedded

processor that has an SPI-compatible interface. In this example,

the SPI master uses an interrupt service routine to collect data

every time the data ready (DR) signal pulses.

Additional information on ADIS16467 SPI can be found in the

Applications Information section of this datasheet.

SYSTEM

PROCESSOR

SPI MASTER

VDD

INPUT/OUTPUT LINES ARE COMPATIBLE WITH

3.3V LOGIC LEVELS

SCLK

DIN

DOUT

SCLK

MOSI

IRQ

MISO

ADIS16467

+3.3V

Figure 26. Electrical Connection Diagram

Table 6. Generic SPI Master Pin Mnemonics and Functions

Mnemonic

Function

Slave select

SCLK

Serial clock

MOSI

Master output, slave input

MISO

Master input, slave output

IRQ

Interrupt request

Embedded processors typically use control registers to configure

serial ports for communicating with SPI slave devices, such as

the ADIS16467. Table 7 provides a list of settings that describe

the SPI protocol of the ADIS16467. The initialization routine

of the master processor typically establishes these settings using

firmware commands to write them into the control registers.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

ADIS16467 operates as slave

SCLK ≤ 2 MHz1

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB First Mode

Bit sequence, see Figure 31 for coding

16-Bit Mode

Shift register and data length

1 A burst mode read requires this value to be ≤1 MHz (see Table 2 for more

information).

DATA READY (DR)

The factory default configuration provides users with a DR signal

on the DR pin (see Table 5) that pulses when the output data

registers update. Connect the DR pin to a pin on the embedded

processor to trigger data collection, on the second edge of this

pulse. Register MSC_CTRL, Bit 0 (see Table 105), controls the

polarity of this signal. In Figure 27, Register MSC_CTRL, Bit 0 = 1,

which means that data collection must start on the rising edges

of the DR pulses.

ACTIVE

INACTIVE

Figure 27. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)

During the start-up and reset recovery processes, the DR signal

may exhibit some transient behavior before data production

begins. Figure 28 shows an example of the DR behavior during

startup, and Figure 29 and Figure 30 provide examples of the

DR behavior during recovery from reset commands.

VDD

START-UP TIME

TIME THAT VDD > 3V

PULSING INDICATES

DATA PRODUCTION

Figure 28. Data Ready Response During Startup

RESET RECOVERY TIME

SOFTWARE RESET COMMAND

GLOB_CMD[7] = 1

DR PULSING

RESUMES

Figure 29. Data Ready Response During Reset

(Register GLOB_CMD, Bit 7 = 1) Recovery

RST

RESET RECOVERY TIME

RST PIN

RELEASED

DR PULSING

RESUMES

Figure 30. Data Ready Response During Reset (RST = 0) Recovery

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