ACE24AC16C datasheet(7/20 Pages) ACE

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ACE24AC16C

Two-wire Serial EEPROM

VER 1.1

The least significant 4 bits of the word address (column address) increments internally by one after

receiving each data word. The rest of the word address bits (row address) do not change internally,

but pointing to a specific memory row or page to be programmed. The first page write data word can

be of any column address. Up to 16 data words can be loaded into a page.

If more than 16 data

words are loaded, the 17th data word will be loaded to the 1st data word column address. The 18th

data word will be loaded to the 2nd data word column address and so on. In other word, data word

address (column address) will “roll” over the previously loaded data.

(C)

Acknowledge Polling

ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal

programming. By issuing a valid read or write address command, the EEPROM will not acknowledge

at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the

programming completes and the chip has returned to the STANDBY mode, the device will return a

valid ACKNOWLEDGE signal at the 9th clock cycle.

Read Operations

The read command is similar to the write command except the 8th read/write bit in address word is set to

“1”. The three read operation modes are described as follows:

(A)

Current Address Read

The EEPROM internal address word counter maintains the last read or write address plus one if the

power supply to the device has not been cut off. To initiate a current address read operation, the

micro-controller issues a start bit and a valid device address word with the read/write bit (8th) set to

“1”. The EEPROM will response with an acknowledge signal on the 9th serial clock cycle. An 8-bit

data word will then be serially clocked out. The internal address word counter will then automatically

increase by one. For current address read the micro-controller will not issue an acknowledge signal

on the 18th clock cycle. The micro-controller issues a valid stop bit after the 18th clock cycle to

terminate the read operation. The device then returns to standby mode.

(B)

Sequential Read

The sequential read is very similar to current address read. The micro-controller issues a start bit

and a valid device address word with read/write bit (8th

) set to “1”. The EEPROM will response with

an acknowledge signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked

out. Meanwhile the internally address word counter will then automatically increase by one. Unlike

current address read, the micro-controller sends an acknowledge signal on the 18th clock cycle

signaling the EEPROM device that it wants another byte of data. Upon receiving the acknowledge

signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal

address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal

on the 27th clock cycle. Another 8-bit data word will then be serially clocked out.

ACE24AC16C Datasheet(PDF) 7 Page - ACE Technology Co., LTD.

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