MPC5601PEF0MLH4R datasheet(18/95 Pages) NXP

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MPC5602P Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

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Trigger generation unit configurable in sequential mode or in triggered mode

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Each trigger can be appropriately delayed to compensate the delay of external low pass filter

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Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

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Double buffered ADC command list pointers to minimize ADC-trigger unit update

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Double buffered ADC conversion command list with up to 24 ADC commands

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Each trigger capable of generating consecutive commands

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ADC conversion command allows to control ADC channel, single or synchronous sampling, independent result queue

selection

1.5.28

Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE-ISTO 5001-2003 standard. This

development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NDI

block is an integration of several individual Nexus blocks that are selected to provide the development support interface for this

device. The NDI block interfaces to the host processor and internal busses to provide development support as per the

IEEE-ISTO 5001-2003 Nexus Class 1 standard. The development support provided includes access to the MCU’s internal

memory map and access to the processor’s internal registers.

The NDI provides the following features:

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Configured via the IEEE 1149.1

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All Nexus port pins operate at VDDIO (no dedicated power supply)

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Nexus Class 1 supports Static debug

1.5.29

Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:

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Support for CRC-16-CCITT (x25 protocol):

— x16 + x12 + x5 + 1

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Support for CRC-32 (Ethernet protocol):

— x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

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Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

1.5.30

IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent

to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format.

The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

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IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

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Selectable modes of operation include JTAGC/debug or normal system operation.

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5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

— IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

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5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

MPC5601PEF0MLH4R Datasheet(PDF) 18 Page - NXP Semiconductors

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