®

AS4LC256K16EO

4/11/01; V.1.1

Alliance Semiconductor

P. 2 of 25

Functional description

The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as

262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative

design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.

The AS4LC256K16EO features a high speed page mode operation in which high speed read, write and read-write are

performed on any of the 512

× 16 bits defined by the column address. The asynchronous column address uses an extremely

to output access time eases system design.

Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the

following:

•RAS-only refresh cycles

• Hidden refresh cycles

•CAS-before-RAS refresh cycles

• Normal read or write cycles

• Self refresh cycles

The AS4LC256K16EO is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely

available automated testing and insertion equipment. System level features include single power supply of 3.3V

± 0.3V

tolerance and direct interface with TTL logic families.

Logic block diagram

Recommended operating conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

3.03.3

3.6V

GND

0.0

0.0

0.0

V

Input voltage

2.0

–

V

–1.0

–

0.8

V

512×512×16

ARRAY

(4,194,304)

SENSE AMP

A0

A1

A2

A3

A4

A5

A6

A7

GND

A8

COLUMN DECODER

RAS CLOCK

GENERATOR

SUBSTRATE

BIAS

GENERATOR

DATA

I/O

BUFFER

OE

RAS

UCAS

WE CLOCK

GENERATOR

WE

LCAS

I/O0 to I/O15

CAS CLOCK

GENERATOR