ATWILC3000A datasheet(21/56 Pages) MICROCHIP

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Table 7-2. SPI Client Interface Pin Mapping

Pin #

SPI Function

CFG: Must be connected to VDDIO

SCK: Serial Clock

TXD: Serial Data Transmit (MISO)

SSN: Active-Low Client Select

RXD: Serial Data Receive (MOSI)

When the SPI is not selected, that is, when SSN is high, the SPI interface will not interfere with data transfers

between the serial host and other serial client devices. When the serial Client is not selected, its transmitted data

output is buffered, resulting in a high-impedance drive onto the serial Host receive line.

The SPI Client interface responds to a protocol that allows an external Host to read or write any register in the chip

and initiate DMA data transfers.

The SPI Client interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase

(CPHA) settings. These modes are illustrated in the following table.

Table 7-3. SPI Client Modes

Mode

CPOL

CPHA

0(1)

Note:

The ATWILC3000A firmware uses “SPI Mode 0” to communicate with the host.

The red lines in the following figure correspond to the Clock Phase at 0 and the blue lines correspond to the Clock

Phase at 1.

Figure 7-2. SPI Client Clock Polarity and Clock Phase Timing

ATWILC3000A

External Interfaces

Datasheet

DS70005427B-page 21

ATWILC3000A Datasheet(PDF) 21 Page - Microchip Technology