SL3S1205FUD2SLASHHA datasheet(13/38 Pages) NXP

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NXP Semiconductors

SL3S1205_15

UCODE 8/8m

Au pads

Pad material

> 99.9 % pure Au

Pad hardness

35 – 80 HV 0.005

Pad shear strength

> 70 MPa

Pad height

3 μm

Pad height uniformity

– within a die

max. 2 μm

– within a wafer

max. 4 μm

Pad flatness

max. 3 μm

Pad size

– RF1, RF2 (max. details see wafer layout)

151.5 μm × 278 μm

– TP1, TP2 (max. details see wafer layout)

134.2 μm × 100 μm

Pad size variation

± 5 μm

Table 4. 12 inch specification with Large Pads, conventional dicing ...continued

Wafer

Designation

each wafer is scribed with batch number and

wafer number

Diameter

300 mm (12") unsawn

Thickness

120 μm ± 15 μm

Number of pads

Pad location

non-diagonal / placed in chip corners

Process

CMOS 0.14 μm

Batch size

25 wafers

Net printed dies per wafer

296307

Wafer backside

Material

Treatment

ground and stress release

Roughness

Ra max. 0.5 μm, Rt max. 5 μm

Chip dimensions

Die size excluding scribe

0.461 mm × 0.471 mm = 0.22 mm2

Scribe line width:

x-dimension = 6.6 μm

y-dimension = 6.6 μm

Passivation on front

Type

Sandwich structure

Material

PE-Oxide (on top)

Thickness

2.25 μm total thickness of passivation

Table 5. 12 inch specification with Large Pads, plasma dicing

SL3S1205_15

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.5 — 1 April 2021

COMPANY PUBLIC

398435

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