Z8F082ASH020SC datasheet(110/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

UART

Z8 Encore! XP® F08xA Seriess

Product Specification

asserts at least one UART bit period and no greater than two UART bit periods before the

Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver

Enable signal deasserts one system clock period after the final Stop bit is transmitted. This

one system clock delay allows both time for data to clear the transceiver before disabling

it, as well as the ability to determine if another character follows the current character. In

the event of back to back characters (new data must be written to the Transmit Data Regis-

ter before the previous character is completely transmitted) the DE signal is not deasserted

between characters. The Depol bit in the UART Control Register 1 sets the polarity of the

Driver Enable signal.

Figure 13.UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)

The Driver Enable to Start bit setup time is calculated as follows:

UART Interrupts

The UART features separate interrupts for the transmitter and the receiver. In addition,

when the UART primary functionality is disabled, the Baud Rate Generator can also func-

tion as a basic timer with interrupt capability.

Transmitter Interrupts

The transmitter generates a single interrupt when the Transmit Data Register Empty bit

(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-

mission. The TDRE interrupt occurs after the Transmit shift register has shifted the first

bit of data out. The Transmit Data register can now be written with the next character to

send. This action provides 7 bit periods of latency to load the Transmit Data register

before the Transmit shift register completes shifting the current character. Writing to the

UART Transmit Data register clears the TDRE bit to 0.

Start

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Parity

Data Field

lsb

msb

Idle State

of Line

Stop Bit

Baud Rate (Hz)

-------------------------------------

⎝⎠

⎛⎞

DE to Start Bit Setup Time (s)

Baud Rate (Hz)

-------------------------------------

⎝⎠

⎛⎞

≤≤

Z8F082ASH020SC Datasheet(PDF) 110 Page - Zilog, Inc.

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