Z8F082ASH020SC datasheet(138/244 Pages) ZILOG

138 / 244 page

PS024705-0405

P R E L I M I N A R Y

Analog-to-Digital Converter

Z8 Encore! XP® F08xA Series

Product Specification

120

100 = Differential, unbuffered input

101 = Differential, buffered input with unity gain

110 = Reserved

111 = Differential, buffered input with 20x gain

ADC Data High Byte Register

The ADC Data High Byte register contains the upper eight bits of the ADC output. The

output is an 11-bit two’s complement value. During a single-shot conversion, this value is

invalid. Access to the ADC Data High Byte register is read-only. Reading the ADC Data

High Byte register latches data in the ADC Low Bits register.

ADCDH—ADC Data High Byte

This byte contains the upper eight bits of the ADC output. These bits are not valid during a

single-shot conversion. During a continuous conversion, the most recent conversion out-

put is held in this register. These bits are undefined after a Reset.

ADC Data Low Bits Register

The ADC Data Low Byte register contains the lower bits of the ADC output as well as an

overflow status bit. The output is a 11-bit two’s complement value. During a single-shot

conversion, this value is invalid. Access to the ADC Data Low Byte register is read-only.

Reading the ADC Data High Byte register latches data in the ADC Low Bits register.

ADCDL—ADC Data Low Bits

These bits are the least significant three bits of the 11-bits of the ADC output. These bits

are undefined after a Reset.

Table 72. ADC Data High Byte Register (ADCD_H)

BITS

FIELD

ADCDH

RESET

XXX

R/W

RRR

ADDR

F72H

Table 73. ADC Data Low Bits Register (ADCD_L)

BITS

FIELD

ADCDL

Reserved

OVF

RESET

XXX

R/W

RRR

ADDR

F73H

Z8F082ASH020SC Datasheet(PDF) 138 Page - Zilog, Inc.

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