PD70224 datasheet(18/30 Pages) MICROCHIP

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Number

Pin Name

(PD70210A)

Pin Name

(PD70210)

Description

4P_HD_FLAG

Open drain output. This pin gets actively pulled low when

a 4-pair HDBaseT PD-PSE mutually identifies each other

through classification. In PD70210A, there is a minimum

80 ms delay from the moment that the input capacitor is

fully charged to this signal activity. In PD70210, this flag

asserts once inrush current is ended. Signal is referenced

to VPN_OUT.

WA_EN

While this input is low (referenced to VPN_IN), the chip

works according to internal flow diagram. When this input

is high, it enables the wall adapter feature. Place from

100 nF/10 V to 1 μF/10 V capacitor from WA_EN to

VPN_IN pins, close to the device. When WA_EN is not

used, connect it to VPN_IN. For more information, see

Figure 1-3.

PGOOD

Open drain output. Power good output signal from the

front-end stage. This pin gets actively pulled low when

power-on occurs. There is a minimum 80 ms delay from

the moment VPort exceeds UVLO ( ~36 V) to this

PGOOD signal being driven low as per the IEEE

standard, to allow the PSE to increase its current limit

after power-up is completed. Signal is referenced to

VPN_OUT.

VAUX

Auxiliary voltage rail. This can be used to provide a few

mA of startup current for the PWM controller (typically,

10.5 V). Signal is referenced to VPN_OUT and is

activated once the front-end power-up sequence ends.

DC-DC must not start up until Vaux is active.

EPAD

Connected on PCB plane to VPN_IN.

The following table lists the pin descriptions for the PD70210AL device.

Table 3-2. PD70210AL Pin Descriptions

Pin Number

Pin Name

Description

1, 2

SUPP_S1

Input pin for sensing the voltage on the diode bridge connected to the data

pairs. This pin, along with the SUPP_S2 pin, can be used to distinguish

between 2-pair and 4-pair operation for PSEs that operate in 4-pairs but do

not generate the classification procedure on both pairs, but one pair only.

Signal is referenced to VPN_IN. Place a 10 KΩ resistor in the input of this

pin.

SUPP_S2

Input pin for sensing the voltage on the diode bridge connected to the data

pairs. This pin, along with the SUPP_S1 pin, can be used to distinguish

between 2-pair and 4-pair operation for PSEs that operate in 4-pairs but do

not generate the classification procedure on both pairs, but one pair only.

Signal is referenced to VPN_IN. Place a 10 KΩ resistor in the input of this

pin.

5,6

PD70210/PD70210A/PD70210AL

Pin Descriptions

Datasheet

DS00003695A-page 18

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