The following figure shows the functional blocks of the PD70210A/PD70210AL devices.

Figure 1-2. PD70210A/PD70210AL Functional Block Diagram

RDET

2/38

RCLS

6/8

VPP

1/35

SUPP_S1

SUPP_S2

3

4

VPN_IN

7/11

8/12

15/28

WA_EN

4P_AT_FLAG

13/26

HD_FLAG

12/25

AT_FLAG

11/24

4P_HD_FLAG

14/27

VPN_OUT

9/16

10/17

Enhanced

Classification

Block

Startup/Inrush

Control

VAUX

16/31

10.5 V

Regulator

4.8 V

Regulator

Vdd

45 mA

1.2 V

Bandgap

Bleeder

Control

Detection

Control

RREF

5/7

Iclass

Class

Control

48 V

48 VRTN

Rsense

PD70210A/PD70210AL

80 ms

Delay Timer

VPP UVLO

VPP UVLO

1.1

Application Information

This section describes the PD70210/A/AL application.

For latest recommendations, contact Microchip and/or see AN3468 Designing a Type 1/2 802.3 or HDBaseT Type 3

Powered Device Front-End Using PD702x0 and PD701x0 ICs.

1.2

Wall Adapter Mode (PD70210A/AL)

PD70210A and PD70210AL supports wall adapter functionality. By setting the WA_EN pin high, it gives priority to the

wall adapter jack to supply the load.

The WA_EN pin is used while connecting a wall-adapter voltage between VPP and VPN_OUT by OR-ing diode.

When WA_EN (the wall adapter enable pin) is held low (referenced to VPN_IN), the front-end works as a normal PD.

When WA_EN is raised high (referenced to VPN_IN), the following three internal operations are forced.

• The isolation FET is turned off.

• All output flags (AT_FLAG, HD_FLAG, 4P_AT_FLAG, and 4P_HD_FLAG) are activated (low state).

• Vaux output voltage is turned on.

While activating the WA_EN pin, the wall adapter supplies input voltage for the DC–DC converter. The WA_EN at a

high state disables the detection and classification modes.

PD70210/PD70210A/PD70210AL

Functional Descriptions

Datasheet

DS00003695A-page 6