SH7041A datasheet(550/923 Pages) RENESAS

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In receiving, the SCI operates as follows:

1.The SCI monitors the communication line.When it detects a start bit (0), the SCI synchronizes

internally and starts receiving.

2.Receive data is shifted into the RSR in order from the LSB to the MSB.

3.The parity bit and stop bit are received.After receiving these bits, the SCI makes the following

checks:

a.Parity check.

The number of 1s in the receive data must match the even or odd parity

setting of the O/E bit in the SMR.

b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit

is checked.

c.Status check.

RDRF must be 0 so that receive data can be loaded from the RSR into the

RDR.

If the data passes these checks, the SCI sets RDRF to 1 and stores the received data in the

RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 14.11.

Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF

bit is not set to 1, so be sure to clear the error flags.

4.After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the

SCR, the SCI requests a receive-data-full interrupt (RxI). If one of the error flags (ORER,

PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also

set to 1, the SCI requests a receive-error interrupt (ERI).

Figure 14.9 shows an example of SCI receive operation in the asynchronous mode.

Table 14.11 Receive Error Conditions and SCI Operation

Receive Error

Abbreviation

Condition

Data Transfer

Overrun error

ORER

Receiving of next data ends while

RDRF is still set to 1 in SSR

Receive data not loaded

from RSR into RDR

Framing error

FER

Stop bit is 0

Receive data loaded from

RSR into RDR

Parity error

PER

Parity of receive data differs from

even/odd parity setting in SMR

Receive data loaded from

RSR into RDR

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