SH7041A datasheet(551/923 Pages) RENESAS

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TDRF

FER

Framing error

generates

ERI interrupt

request.

1 frame

RxI interrupt

handler reads

data in RDR and

clears RDRF to 0.

0/1

Parity

bit

Parity

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle

(marking

state)

0/1

RxI interrupt request

Example: 8-bit data with parity and one stop bit.

Figure 14.9 SCI Receive Operation

14.3.3

Multiprocessor Communication

The multiprocessor communication function enables several processors to share a single serial

communication line for sending and receiving data. The processors communicate in the

asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format).

In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial

communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a

data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending

cycles. The transmitting processor starts by sending the ID of the receiving processor with which it

wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor

sends transmit data with the multiprocessor bit cleared to 0.

Receiving processors skip incoming data until they receive data with the multiprocessor bit set to

1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the

data with their IDs. The receiving processor with a matching ID continues to receive further

incoming data. Processors with IDs not matching the received data skip further incoming data

until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and

receive data in this way.

Figure 14.10 shows the example of communication among processors using the multiprocessor

format.

SH7041A Datasheet(PDF) 551 Page - Renesas Technology Corp

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