SH7041A datasheet(555/923 Pages) RENESAS

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TDRE

TEND

TxI interrupt

handler writes

data in TDR and

clears TDRE to 0

TxI

interrupt

request

TEI

interrupt

request

1 frame

0/1

Multiprocessor

bit

Multiprocessor

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle

(marking

state)

0/1

Example: 8-bit data with multiprocessor bit and one stop bit

TxI

interrupt

request

Figure 14.12 SCI Multiprocessor Transmit Operation

Receiving Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for receiving

multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below.

1.SCI initialization: Set the RxD pin using the PFC.

2.ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1.

3.SCI status check and compare to ID reception: Read the serial status register (SSR), check that

RDRF is set to 1, then read data from the receive data register (RDR) and compare with the

processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and clear

RDRF to 0. If the ID matches the receive data, clear RDRF to 0.

4.Receive error handling and break detection: If a receive error occurs, read the ORER and FER

bits in SSR to identify the error. After executing the necessary error processing, clear both

ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a

framing error occurs, the RxD pin can be read to detect the break state.

5.SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data

from the receive data register (RDR).

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